Espressif Systems /ESP32-S3 /UHCI0 /INT_ENA

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Interpret as INT_ENA

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RX_START_INT_ENA)RX_START_INT_ENA 0 (TX_START_INT_ENA)TX_START_INT_ENA 0 (RX_HUNG_INT_ENA)RX_HUNG_INT_ENA 0 (TX_HUNG_INT_ENA)TX_HUNG_INT_ENA 0 (SEND_S_REG_Q_INT_ENA)SEND_S_REG_Q_INT_ENA 0 (SEND_A_REG_Q_INT_ENA)SEND_A_REG_Q_INT_ENA 0 (OUTLINK_EOF_ERR_INT_ENA)OUTLINK_EOF_ERR_INT_ENA 0 (APP_CTRL0_INT_ENA)APP_CTRL0_INT_ENA 0 (APP_CTRL1_INT_ENA)APP_CTRL1_INT_ENA

Description

Interrupt enable bits

Fields

RX_START_INT_ENA

This is the interrupt enable bit for UHCI_RX_START_INT interrupt.

TX_START_INT_ENA

This is the interrupt enable bit for UHCI_TX_START_INT interrupt.

RX_HUNG_INT_ENA

This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt.

TX_HUNG_INT_ENA

This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt.

SEND_S_REG_Q_INT_ENA

This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT interrupt.

SEND_A_REG_Q_INT_ENA

This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT interrupt.

OUTLINK_EOF_ERR_INT_ENA

This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt.

APP_CTRL0_INT_ENA

This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt.

APP_CTRL1_INT_ENA

This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt.

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